1. Technical Field of the Invention
The present invention relates to a bit-line sense amplifier for sensing and amplifying data in a semiconductor memory to output them and, more particularly, to a bit-line sense amplifier capable of modifying an amplification method in a sequential manner by using switching elements controlled by switching control signals to compensate an offset voltage of the sense amplifier.
2. Discussion of Related Art
Typically, a bit-line sense amplifier senses and amplifies data on a bit-line to output them on a data bus, and a data bus sense amplifier senses and amplifies the data amplified by the bit-line sense amplifier again to output them to a data output buffer. Usually, a cross-coupled latch type amplifier is used as the bit-line sense amplifier.
Now, operations of the typical bit-line sense amplifier will be described with reference to FIG. 1 as follows. First, transistors Q1 to Q3 are turned on depending on a bit-line precharge signal BLP, so that bit-lines Bit and /Bit are precharged by a precharge voltage (e.g., VBLP). As a result, the bit-line Bit connected to a selected memory cell and a complementary bit-line /Bit are equalized.
A row decoder analyzes a row address input from the external to select a word-line corresponding to the row address. Then, a cell transistor connected to the selected word-line is turned on, so that a potential difference occurs between the bit-line Bit connected to the selected memory cell and the complementary bit-line /Bit, while charge sharing occurs between a cell capacitance and a bit-line capacitance.
At this moment, when a sense amplifier control signals RTO and /S are enabled, a sense amplifier control signal is at a high level. When a sense amplifier control signal /S is at a low level, a bit-line sense amplifier operates to sense the potential difference between the bit-line Bit and the complementary bit-line /Bit and then amplify it.
For example, when the data stored in a selected memory cell corresponds to a low level data, the potential of the bit-line Bit connected to the selected cell comes to be lower than the precharge voltage, and the potential of the bit-line /Bit which is not connected to the selected cell remains at a precharge voltage, thereby generating a potential difference between two bit-lines.
Consequently, in the bit-line sense amplifier corresponding to a cross-coupled latch type amplifier, the transistors Q5 and Q6 are turned on, while the transistors Q4 and Q7 are turned off, so that the bit-line Bit connected to the selected memory cell is at a low level by the sense amplifier control signal /S. On the other hand, the complementary bit-line /Bit is at a low level by the sense amplifier control signal RTO.
Subsequently, a column address is analyzed by a column decoder, and then the data on the bit-line amplified by the bit-line amplifier are sent to a data bus if a column control signal corresponding to the column address is enabled at a high level.
Nevertheless, if such a sense amplifier in a conventional semiconductor memory device operates at a lower voltage, a safe operation cannot be ensured when the data on the bit-line are sensed by the offset voltage between the bit-line and the sense amplifier. Therefore, there have been problems such as excessive time consumption to sufficiently amplify the data on the bit-line.
This is because, if the bit-line sense amplifier operates at a lower voltage, the amount of charges stored in a memory cell can be reduced, so that the potential difference between the bit-line connected to a memory cell and the complementary bit-line is reduced during the charge sharing.
As a consequence, when a bit-line sense amplifier senses a small potential difference between the bit-line connected to the selected memory cell and the complementary bit-line, the sense amplifier can operate slower because the potential difference is almost the same as the offset voltage. Furthermore, data errors can occur because the data can be incorrectly sensed if the difference is smaller than the offset voltage.
FIG. 2 shows a conventional bit-line sense amplifier for solving the above problems, and will be described with reference to FIG. 3.
A time period T0 in FIG. 3 is a preparation stage for driving a sense amplifier. In the time period T0, a precharge signal BLP is enabled at a high level before a semiconductor memory device performs a read or a write operation, so that transistors NM4 and NM5 are turned on. As a result, the bit-lines BL and /BL are precharged by a precharge voltage VBLP.
In addition, in order to eliminate a voltage difference between the bit-lines BL and /BL, an equalization control signal EQ is enabled at a high level, so that a transistor NM1 is turned on and the bit-lines BL and /BL are interconnected to be equalized. At this moment, a sense amplifier control signal /S is also precharged by the precharge voltage VBLP according to the same method.
During the time periods T1 to T4, a sense amplifier 40 is enabled. In addition, the sense amplifier 40 is sequentially modified in each time period depending on the control signals CONA, CONB, and CONC, so as to be a negative feedback differential amplification scheme in a time period T1, a normal differential amplification scheme in a time period T2, a positive feedback differential amplification scheme in a time period T3, and a cross-coupled latch type amplification scheme in a time period T4 in that order.
In the time period T1, the precharge control signal BLP is disabled at a low level and the sense amplifier control signal /S is enabled at a low level, so that the sense amplifier 40 begins to operate. At this moment, since the switching control signals CONA and CONB are at a low level, the PMOS transistor PM3 is turned on, so that the gate of the PMOS transistor PM1 is commonly connected to the drain. As a result, the sense amplifier 40 constitutes a differential amplifier.
In addition, since a switching control signal CONC is at a high level, the NMOS transistor NM13 is turned on, so that the complementary bit-line line /BL corresponding to the inverted input terminal of the sense amplifier 40 is connected to the drain to which the PMOS transistor PM2 corresponding to an output terminal of the sense amplifier 40 and the NMOS transistor NM9 are commonly connected. As a result, the sense amplifier 40 constitutes a negative feedback differential amplifier. Accordingly, the potential of the complementary bit-line /BL is adjusted to a voltage capable of compensating the offset voltage of the sense amplifier 40.
Subsequently, in the time period T2, the switching control signal CONC is at a low level, so that the NMOS transistor NM13 is turned off, and all other switching control signals CONA and CONB remain at a low level. As a result, the sense amplifier 40 constitutes a normal differential amplifier. At this moment, the word-line WL is enabled, so that the data stored in the selected memory cell is loaded on the bit-line BL. Therefore, the data on the bit-line BL are sensed and amplified by the normal differential amplifier.
In the time period T1, because the offset voltage of the. differential amplifier has been compensated, even though a small amount of signal voltage is applied to the bit-line BL, it can be rapidly sensed and amplified by the differential amplifier.
Subsequently, in the time period T3, the switching control signal CONB comes to be a high level, and the NMOS transistor NM11 is turned on, so that the bit-line BL corresponding to the non-inverted input terminal of the sense amplifier 40 is connected to the drain to which the PMOS transistor PM2 corresponding to an output terminal of the sense amplifier 40 and the NMOS transistor NM9 are commonly connected, while other switching control signals CONA and CONC remain at a low level. As a result, the sense amplifier 40 constitutes a positive feedback differential amplifier. For this reason, the data on the bit-line BL is converted to a large intensity of signal by the action of the positive feedback differential amplifier.
Subsequently, in the time period T4, the switching control signal CONA is at a high level, so that the PMOS transistor PM3 is turned off, and the NMOS transistors NM10 and NM12 are turned on. In addition, the switching control signal CONB is at a high level so that the NMOS transistor NM11 is turned on, while the switching control signal CONC remains at a low level so that the NMOS transistor NM13 remains to be turned off. As a result, the sense amplifier 40 constitutes a cross-coupled latch. Therefore, it is possible to rapidly latch the data that have been amplified in the previous stage T3. At this moment, the column selection signal YI is enabled to be at a high level, so that the latched data are output to the data buses DB and /DB.
Among the above processes, the mechanism of the offset voltage compensation in the time period T1 will be described in detail as follows. That is, the bit-line sense amplifier in FIG. 2 is temporarily modified to be a differential amplifier as shown in FIG. 4A, in the time period T1. At this moment, the offset voltage can be compensated by shorting input/output terminals of the differential amplifier for a predetermined time period. The operation of such a differential amplifier will be described in detail with reference to FIGS. 4A and 4B.
When an inverted (−) input terminal and the output of the differential amplifier are shorted in an instant, the differential amplifier is modified to operate as a negative feed back differential amplifier and function in such a way that the input offset voltage can be cancelled. If a voltage gain of the differential amplifier is sufficiently large, the differential voltage between the input terminals becomes an input offset voltage of the differential amplifier in a predetermined time after the shorting, so that offset compensation can be achieved and its sensitivity can be improved.
However, as a wafer scaling progresses to improve integrity, the output resistance of the MOSFET is reduced, and the voltage gain of the differential amplifier is also reduced correspondingly.
If the voltage gain A of the differential amplifier is not sufficiently large, the offset compensation effect of the bit-line sense amplifier is significantly affected by the difference between the precharge level (Vin, typically ½ VDD) of a differential input amplifier and the output voltage level Vo of a differential amplifier with no offset.
A residual offset after the offset compensation in the bit-line sense amplifier can be expressed by the following equation;
                              V          offe                =                                            V              off                        +                          V              in                        -                          V              o                                            1            +            A                                              [                  Equation          ⁢                                          ⁢          1                ]            
FIG. 5 shows a residual offset voltage according to a voltage gain of the differential amplifier and an output voltage level of the differential amplifier. It is possible to recognize that the residual offset can be considerably large depending on the difference between the output voltage level and the input voltage level. For example, if the voltage gain is set to 10, the difference between the input voltage and the output voltage is set to 200 mV, and an original input offset voltage is set to 50 mV, the residual offset voltage becomes 23 mV, so that 45% of the original offset voltage still remains to be not compensated.
For another example showing the residual offset voltage problem, FIG. 6 is a graph showing bit-line signal components in a variety of configurations and array arrangements. The bit-line signals are composed of an effective read signal A, a residual offset voltage B, and a charge noise C. As seen from FIG. 6, the residual offset voltage based on design conditions is set to about 10 to 20 mV, and the original offset voltage is set to 40 mV, which correspond to 25 to 50% of the bit-line signals.
Accordingly, in order to reduce the residual offset voltage and maximize the offset compensation effect, the output voltage level of the differential amplifier should be designed to correspond with the precharge level of the differential input. However, the output voltage level of the differential amplifier is affected by the threshold voltage variations in the input NMOS transistor or the PMOS transistor, and geometrical variations in the channel length or width, thereby causing inconsistency with the design values. The variation on the output voltage caused by such process variations significantly affects the residual offset voltage of the bit-line sense amplifier.
Such a variation on the output voltage in the differential amplifier will be described with reference to FIGS. 7 and 8 as follows.
The differential amplifier comprises PMOS transistors P1 and P2 and NMOS transistors N1, N2, and N3, which constitute a current mirror. The PMOS transistors P1 and P2 correspond to active resistors, and the NMOS transistor N3 corresponds to a current source. When an identical voltage is applied to the input terminals IN and /IN, in case of an ideal differential amplifier, the current through the NMOS transistor N1 becomes identical to that through the NMOS transistor N2.
The curve C1 in FIG. 8 designates a current driving capability of the PMOS transistor based on design values, and the curve C2 designates a current driving capability of the PMOS transistor based on a practical case. As shown in the graph, the practical current driving capability of the PMOS transistor is lower than that of the design values due to process variations. This causes a variation on the output voltage level. In other words, despite the fact that the output voltage should reach Vo2 according to the design value, the output voltage remains at Vo1 which is lower than Vo2 due to the variation on the current driving capability.